The present invention relates to a semiconductor device and a manufacturing technology thereof, and, relates to a technology effectively applicable to, for example, a semiconductor device in which over a semiconductor chip, there is mounted another semiconductor chip.
In Japanese Unexamined Patent Publication No. 2011-187574 (Patent Document 1), there is described a semiconductor device in which a semiconductor chip including through electrodes is arranged between a lamination of a plurality of memory chips and a wiring substrate.
Further, in Japanese Unexamined Patent Publication No. 2010-118522 (Patent Document 2), there is described a semiconductor device which has solder bumps for electrically connecting oppositely arranged electrodes with each other, and in which the solder bumps are connected with a plurality of portions of each of the electrodes.